The present invention relates to a structure of an integrated circuit component and its producing methods and, more particularly, to a low electric field source erasable non-volatile memory and methods for producing the low electric field source erasable non-volatile memory.
Non-volatile memories have advantages of small volumes, light weights, low power consumption, and prevention of loss of data resulting from power interruption and are, thus, suitable for applications in hand-held electronic devices. Following the popularization of hand-held electronic devices, non-volatile memories have widely been used as multimedia storage devices or used for maintaining normal operation of electronic systems. The need of non-volatile memories increases every year, and the costs and prices decrease, which is a positive cycle for non-volatile memories. Thus, non-volatile memories have become one of the most important products in the semiconductor industry.
U.S. Pat. No. 4,698,787 discloses an erasable non-volatile memory unit of a stack-gate non-volatile memory structure including a floating gate. When the memory undergoes an operation of writing “1”, a sufficient amount of electrons is trapped in the floating gate by hot-electron injection, such that the status of the memory unit is “1”. When the memory undergoes an operation of writing “0” or erasing, electrons are removed from the floating gate by Fowler-Nordheim tunneling, such that the status of the memory unit is “0”. Since the status of the memory unit depends on whether a sufficient amount of electrons is trapped in the floating gate, the status of the memory unit can be maintained even if the power source is removed and is, thus, referred to as a non-volatile memory.
However, the stack-gate non-volatile memory still has the following disadvantages. Firstly, an over erasure effect exists. When the memory unit undergoes the erasing operation, excessive electrons could be removed from the floating gate, resulting in a negative threshold voltage of an equivalent transistor component in the memory unit; namely, the memory unit is normally in a conductive state that leads to unnecessary leakage current. Secondly, a larger operating current is required during the erasing operation. When the memory undergoes the erasing operation, the source voltage is much larger than the voltage of the floating gate and, thus, results in a gate-induced drain leakage (GIDL) effect, leading to leakage current from the source to the substrate. As a result, an external power source more powerful in providing current is required in the operation, leading to difficulties in integration of the whole circuit. Furthermore, to reduce the extent of leakage, the source is in the form of a lightly-doped drain structure. However, as the processes are more and more advanced and the size becomes smaller and smaller, the lightly-doped drain is apt to cause a punch-through effect. Thus, when a stack-gate non-volatile memory is produced by a process for less than 0.2 μm technology node, the lightly-doped drain structure is replaced by a deep N-well to isolate the source from the substrate to avoid leakage. However, in a memory matrix comprised of stack-gate non-volatile memories, a plurality of memory units shares the deep N-well to save the area. Due to the structural limitation, the memory units sharing the deep N-well must simultaneously undergo the erasing operation, which sacrifices the operational flexibility of the circuit. Lastly, during writing of “1”, the tunneling probability of electrons is low, because the electric field of the channel is stronger. Thus, a stronger current is required in the operation for increasing the operating speed.
U.S. Pat. No. 5,338,952 and U.S. Pat. No. 5,414,286 disclose a split-gate non-volatile memory. As shown in FIG. 1, in comparison with the above conventional technique, the split-gate non-volatile memory has an additional select gate. Since conduction of the channel in an equivalent transistor component of the non-volatile memory unit requires a positive voltage at both the floating gate and the select gate to be larger than the threshold voltage, the drawback of normal leakage can be avoided by controlling the voltage of the selective gate. Similar to the above conventional stack-gate technique, in order to reduce the gate-induced drain leakage (GIDL), the heavy/light doping of the source is achieved by a diffusing structure of a lightly-doped drain, such that both the gradual heavily-doped region and the lightly-doped region of the source diffuse and are formed below the floating gate to reduce the horizontal electric field of the source, thereby reducing the vertical electric field between the source and the floating gate and thereby reducing the GIDL. However, as the processes are more and more advanced and the size becomes smaller and smaller, the lightly-doped drain is apt to cause a punch-through effect. Thus, the chip has a larger area if the stack-gate non-volatile memory is produced by a process for less than 0.2 μm technology node.
U.S. Pat. No. 7,009,144, U.S. Pat. No. 7,199,424, and U.S. Pat. No. 7,407,857 also disclose a split-gate non-volatile memory structure in which a stepped structure is provided at a bottom of the floating gate. As shown in FIG. 2, in comparison with the conventional technique of the above split-gate non-volatile memory, although the wedge structure cannot completely avoid the GIDL during the erasing operation, the source of the wedge structure extends to the thicker area of the stepped structure of tunnel oxidation layer. Thus, the vertical electric field between the floating gate and the source can greatly be reduced to reduce the GIDL. However, during conduction of an equivalent transistor component of the non-volatile memory unit, the magnitude of the conduction current is decided by a thicker gate dielectric layer formed by the wedge structure, such that the change in the conduction current is larger and, thus, adversely affects the yield of the memories. Furthermore, the thicker tunnel dielectric layer of the stepped floating gate is liable to cause a short circuit between the drain and the source, resulting in great limitation to further miniaturization of the structure.